The invention relates to a memory device. More particularly, the invention relates to double exposure technology and a method for forming a pattern in a semiconductor device using the same.
In general, a semiconductor device such as dynamic random access memory (“DRAM”) includes numerous fine patterns. Such patterns are formed through a photolithography process. In order to form a pattern by the photolithography process, a photoresist (“PR”) film is coated over a target layer to be patterned. Next, a conventional exposure process is performed to change the solubility of a given portion of the PR film. Subsequently, a developing process is performed to form a PR pattern exposing the target layer. That is, the PR pattern is formed by removing the portion having an altered solubility, or the portion having an unaltered solubility. Then, the exposed target layer is etched using the PR pattern, and the PR pattern is subsequently stripped to form a target layer pattern.
In the photolithography process, resolution and depth of focus (“DOF”) are two important issues. Resolution (R) can be expressed by Equation 1 below.
                              R          =                                    k              1                        ⁢                          λ              NA                                      ,                            (        1        )            where k1 is a constant determined by the type and thickness of the PR film, λ is the wavelength of the light source, and NA is the numerical aperture of the exposure equipment.
According to Equation 1, the shorter the wavelength (λ) of the light source and the larger the NA of the exposure equipment, the finer the pattern that is formed over a wafer. However, the wavelength (λ) of the light source being used and the NA of the exposure equipment have not kept abreast of advances in the level of integration in semiconductor devices. Therefore, resolution enhancement technology (“RET”) for improving resolution and DOF is applied by incorporating diverse methods. For example, RET technology includes using a phase shift mask (“PSM”), off-axis illumination (“OAI”) optical proximity correction (“OPC”), and the like. Additionally, there is a technology called double exposure technique (“DET”) capable of forming a fine pattern over a wafer. Critical dimension (CD) uniformity in the DET depends on the overall overlay accuracy of a first exposure mask and a second exposure mask.
As the design rules of semiconductor devices shrink, it becomes more difficult to form a fine contact hole due to limitations of the exposure apparatus and the photoresist material. A resist flow process may be an alternative solution to overcome such difficulties. The resist flow process is a technique for forming a contact hole beyond the resolution limit of the exposure apparatus. First, the resist flow process includes patterning a first contact hole with a polymer photoresist through a photolithography process. Afterwards, the photoresist is reheated to a temperature above the glass transition temperature Tg and undergoes thermal flow to form a second contact hole smaller than the first contact hole.
In the method for forming patterns in the semiconductor device employing double exposure technology, the process margin is poor. In addition, the device failure may occur due to the Mask Error Factor (“MEF”).